Prof. Mahapatra’s analysis and modeling methodology, which has been helping semiconductor manufacturers to make reliable electronic chips, is now available as “Mahapatra reliability model” in Sentaurus Device TCAD software from Synopsys.
Semiconductor chips are used everywhere—mobile phones and laptops, washing machines and microwaves, and cars and planes. We need high-performance chips that consume less power. We want to play fast video games and charge our mobiles less often, for example. We need the electronic chips to be reliable—the device should perform as intended over the specified time. We would hate to see our video game stalling after a few months of use.
Semiconductor chips are a few millimetres in size and have dense electrical circuits made up of billions of transistors – the tiny nanosized switches that process, store and transmit data. They are manufactured in a semiconductor fabrication plant (fab), using precise, complex and expensive processes. Thorough analysis and skilful design are needed to identify situations in which chips could fail and to mitigate such failures till the end of a product’s life.
Prof. Souvik Mahapatra of the Department of Electrical Engineering, IIT Bombay has been spearheading the efforts to characterize, understand, model and control transistor reliability for over two decades. He collaborates closely with several leading industries in the semiconductor chip ecosystem, including IBM, Intel, Micron, Applied Materials and Synopsys to name a few. As a result of his effort, the semiconductor industry has a methodology for characterizing and optimizing reliability across various advanced CMOS logic and memory technologies.
During technology development, simultaneous optimization of performance, power and reliability of the transistor is important for delivering robust chips. The performance and power can be readily measured on an already fabricated transistor or a chip. However, reliability involves transistor or chip performance degradation at the end of a product’s life, and estimating it is more complex.
“The degradation of transistor performance at normal operating conditions of a chip becomes appreciable only at a very long time close to the end of product life. Since reliability must be estimated during technology development, short-time accelerated stress tests are done to speed up transistor degradation, and theoretical projection methods are used to estimate its severity at the end-of-life under normal operating conditions”, said Prof. Mahapatra. He added, “Error in the theoretical model can lead to either underestimation or overestimation of degradation during the technology development phase with significant consequences; either the release of a defective product or an unnecessary increase in the expense and time due to overoptimization”.
Dr. Chandra Mouli, Vice President of Device Technology, Micron, USA said, “We have a long and fruitful collaboration with Prof. Mahapatra. He works closely with our technology team as a consultant in the reliability assessment of advanced transistors used in our products. Industry faces several reliability challenges as we continue to push aggressively with technology scaling, requiring us to have a strong focus on understanding transistor wearout and degradation mechanisms, to predictively model the degradation for lifetime assessments. Prof. Mahapatra has a deep interest in understanding practical challenges in technology development and high-volume manufacturing. This combined with his exceptional knowledge in transistor reliability mechanisms makes him unique in the world for such partnership”.
Dr. Mukesh Khare, General Manager of IBM Semiconductors and Vice President, Hybrid Cloud Research at IBM, USA, acknowledges by saying “Over the last several years, IBM has worked closely with Prof. Mahapatra and his students to advance logic technology scaling. Leveraging experimental data from transistors fabricated at IBM’s semiconductor research lab at the Albany NanoTech Complex, Prof. Mahapatra and his team have developed comprehensive reliability models that greatly enhance the accuracy of transistor and circuit ageing projections for advanced technology nodes”.
Dr. Satheesh Kuppurao, Group Vice President of Business Development and Growth in Semiconductor Products Group at Applied Materials, USA, said, “Applied Materials, Inc., one of the world’s leading providers of semiconductor chip fabrication equipment, has closely collaborated with IIT Bombay and Prof. Mahapatra for over the past two decades developing, evaluating, and improving materials and processes used in leading-edge logic and memory technologies. Prof. Mahapatra’s expertise and contributions led to a deep understanding of transistor reliability and degradation mechanisms that resulted in several innovative solutions that were developed and deployed by Applied Materials in leading semiconductor fabs across the world.” The tremendous advances in semiconductor chips can partly be attributed to advancements in the equipment and processes deployed in a fab. Several hundred processes are used to make a chip, and each must be carefully controlled for best results.
During technology development, a semiconductor fab evaluates hundreds of process options before choosing the most optimal one. Since this experimentation is an expensive and timeconsuming process, Technology Computer-Aided Design (TCAD) software is often used to simulate and help eliminate some and choose some of the experimental options. TCAD is traditionally used to simulate performance and power of the transistor. Prof. Mahapatra’s models are now available in TCAD for reliability assessment.
Dr. Victor Moroz, Fellow, Synopsys, USA, said, “Synopsys, a leading provider of TCAD software, has been collaborating with Prof. Mahapatra for the past decade. As a result of this collaboration, a reliability model has been developed and incorporated in Sentaurus Device TCAD (named as “Mahapatra Reliability Model”), which is being used by several industries in the logic and memory areas of the semiconductor ecosystem”. Synopsys has acknowledged Prof. Mahapatra’s achievement with an award, which was given at their event during the International Electron Devices Meeting (IEDM) in San Francisco in December 2024. Dr. Khare of IBM added, “This award is a well-deserved recognition for Prof. Mahapatra, who has been a crucial contributor to advancing semiconductor industry innovation”.
Dr Stephen Ramey, Engineering Manager of Reliability Group at Intel, USA, endorses by saying “It is a great pleasure to learn that Prof. Mahapatra has been considered for an award from Synopsys in recognition of contributions to the physical understanding and modelling of reliability mechanisms in advanced logic transistors. The reliability of these transistors continues to be a key consideration during the development of new technologies, especially in the gate-all-around architecture which significantly affects the underlying physics driving reliability phenomena. At Intel, our long-standing collaboration with Prof. Mahapatra has been instrumental in guiding both the understanding of reliability mechanisms as well as finding paths for the process technology to continue Moore’s law scaling”.